The present invention relates to memory arrays, and more particularly to high speed techniques for reading data from memory arrays.
Prior art memory arrays includes rows and columns of static random access memory cells (SRAM). Each SRAM cell includes two cross coupled inverter circuits that store one bit of data. In a multi-port SRAM, each row of memory cells is coupled to a read word line and a write word line, and each column of memory cells is coupled to a read bit line and a write bit line.
In a single port SRAM, the read word line and the write word line for each row of memory cells are the same. Also, the read bit line and write bit line for each column of memory cells are the same in a single port SRAM.
By activating the write word line for a selected row, a data bit can be written into a selected memory cell in the selected row. The data bit is transmitted to the selected memory cell along the write bit line that controls the selected memory cell.
By activating the read word line for a selected row, a data bit can be read from a selected memory cell in the selected row. The data bit is transmitted from the selected memory cell outside the memory array along the read bit line that controls the selected memory cell.
Once a data bit has been read from a memory cell, the data bit can be buffered and amplified using a differential sense amplifier. Differential sense amplifiers are used to reduce the parasitic effects of noise on output signals from a memory array. Noise can cause a bit to be read incorrectly. For example, noise can cause a logic high to be interpreted as a logic low. Differential amplifiers cancel out the effects of noise on output signals from a memory array.
Sometimes the bit line capacitance is very high. When the bit line capacitance is high, the differential voltage is slow to develop across the differential bit lines. A differential amplifier amplifies the differential bit line signal and results in a faster access time for the memory.
Some prior art memory arrays use inverter circuits to sense the bit line voltage. Because voltages on the bit lines change slowly (due to high capacitances), an inverter is slow to sense the bit line voltage.
The output signals of the inverters are multiplexed by a multiplexer. The multiplexer selects a signal from one of the inverter circuits.
Typically, a single multiplexer in a memory array multiplexes signal from numerous read bit lines. For example, a single multiplexer may multiplex signals from 8 bit lines. Prior art multiplexers are slow to read bits from a memory array, because they have to multiplex signals from many read bit lines. Also, long wires may extend from the outputs of the inverters to the inputs of the multiplexer, further slowing down read time.
Therefore, it would be desirable to provide faster techniques for reading data bits from memory cells in a memory array.